1. Field of the Invention
The invention relates to a system for diagnosing an integrated circuit such as LSI and a method of doing the same, and more particularly to such a system and a method for identifying a failure in an integrated circuit.
2. Description of the Related Art
A failure generated in a CMOS logic circuit has been conventionally identified by virtue of a test using output logic data. Specifically, in the test, a test vector is input into LSI to be tested, through its input terminal, and then, there is obtained output logic data transmitted from LSI through its output terminal. If the thus obtained output logic data is not identical with expectation, a failure site would be identified by means of the number of the test vector, the output logic data and the number of the input and output terminals.
The above-mentioned test is grouped into two groups. The first group is called “back-trace process”, in which logic is traced in an opposite direction, that is, traced back from an output terminal to an input terminal to thereby identify a failure site. The second group is called “failure dictionary process”, in which an output expected by logic simulation as transmitted from LSI in which a failure is in advance defined is checked as to whether it is identical with an output transmitted from LSI actually having a failure therein, and thereby, a failure site is identified in accordance with a result of checking.
FIG. 1 shows how the back-trace process is carried out.
In the back-trace process, as illustrated in FIG. 1, implicative operation is repeatedly carried out in a direction from an output terminal (Pad) to an input terminal for developing logics, to thereby identify a failure site. Herein, the implicative operation means an operation for pursuing unknown logic of a fundamental logic circuit, based on input and output logics of an arbitrary fundamental logic circuit. The implicative operation is grouped into a forward implicative operation for pursuing logic in a direction from an input terminal to an output terminal, and a backward implicative operation for pursuing logic in a direction from an output terminal to an input terminal.
It would be possible to determine logic of connection among fundamental logic circuits, and finally, identify a failure site by means of the above-mentioned implicative operation.
In FIG. 1, it is considered that a failure exists in a conical portion 51 obtained by repeatedly carrying out back-tracing from an output terminal through which abnormal expectation is output, to an input terminal through the use of implicative operation. It would be possible to identify an area in which a failure exists, with a higher accuracy, by defining an area 52 in which a plurality of cones defined based on failure terminals for a plurality of abnormal expectation overlap one another.
FIG. 2 shows how the failure dictionary process is carried out.
In the failure dictionary process, a failure dictionary is used. Herein, a failure dictionary is comprised of a table in which there are listed output data such as the number of terminal, logic and/or timing transmitted by logic simulation from a circuit in which degeneracy failure is defined. In the failure dictionary process, abnormal output expectation transmitted from LSI having a failure therein is compared to a failure dictionary, and if they are identical with each other, the defined degeneracy failure is judged as a failure occurring in the LSI.
The above-mentioned back-trace process is accompanied with the following problems.
First, the back-trace process can find only a logic error, and hence, it is quite difficult or almost impossible to diagnose models other than a degeneracy failure model. That is, the back-trace process is not applicable to failure modes other than a degeneracy failure model.
Second, in the back-trace process, since logic is traced back in a direction from an output terminal to an input terminal, it is impossible to define an end point. In addition, logic development in an opposite direction, that is, in a direction from an output terminal to an input terminal is increased in proportion to a square of the number of devices. Accordingly, it is not possible to converge diagnosis.
Third, the number of routes for retrieval is increased as a scale of integration in LSI is increased, and hence, it is not avoidable to extract a lot of pseudo-failure sites.
The above-mentioned failure dictionary process is accompanied with the following problems.
First, as a scale of integration in LSI is increased, data about failures to be defined would be much increased.
Second, the failure dictionary process makes it possible to find only a logic error, and hence, it is quite difficult or almost impossible to diagnose models other than a degeneracy failure model. That is, the failure dictionary process is not applicable to failure modes other than a degeneracy failure model.
Japanese Unexamined Patent Publication No. 61-155874 (A) has suggested a method of finding a failure in a large-scale integrated circuit, including the steps of setting scan paths for each of functional modules constituting the large-scale integrated circuit, selecting one of the functional modules, based on address data, inputting scan data into a scan path of the thus selected functional module, and finding a failure in the selected functional module, based on an output transmitted through the scan path of the selected functional module.
Japanese Unexamined Patent Publication No. 62-168240 (A) has suggested a scan path circuit including a scan path having flip-flops of a data processor which flip-flops are electrically connected in bit serial to one another, first means for inputting code data into the scan path which code data makes it possible to identify boundaries by which the scan path is divided in the unit of a hardware, second means for finding the code data input into the scan path through the first means, among output data transmitted from the scan path, and counting the number of finding the code data, and third means for controlling shift operation on the scan path, and instructing the first means to input the code data from the boundaries of the scan path.
Japanese Unexamined Patent Publication No. 63-169580 (A) has suggested a scan design circuit including a flip-flop constituting a scan path, a first external output terminal through which data is output from the flip-flop, and a circuit having a second external output terminal, and a switch included in the circuit. Either data to be input through a data-transmitting path or data transmitted from a particular site in the scan path is transmitted to the data-transmitting path through which data is transmitted in normal operation, through the switch.
Japanese Unexamined Patent Publication No. 2-136936 (A) has suggested a data processing system including (a) a processor having logic circuits each having first and second scan path, and a scan path circuit comprised of the first and second scan path electrically connected in series to each other, (b) a diagnostic device for controlling an operation of the scan path circuit to diagnose the data processor, (c) first and second selectors for selectively inputting output signals transmitted from the first and second scan paths, into first and second scan paths in a next stage logic circuit, and an instructor provided in the diagnostic device for instructing the first and second selectors for selection of the output signals.
Japanese Unexamined Patent Publication No. 4-30227 (A) has suggested a circuit comprised of a plurality of flip-flops electrically connected in series to one another to thereby define a scan path. A plurality of the flip-flops are electrically connected to an AND circuit and an OR circuit to thereby define an interactive path. A direction in which scanning is carried out is varied by inputting a control signal into the AND and OR circuits.
Japanese Unexamined Patent Publication No. 5-180908 (A) has suggested a logic integrated circuit including a scan path comprised of a plurality of flip-flops, a combinational circuit providing logic to the flip-flops, and a shift register for storing data therein. The shift register separately receives outputs transmitted from the flip-flops, and defines a scan path other than the above-mentioned scan path.
Japanese Unexamined Patent Publication No. 5-72272 (A) has suggested a logic circuit including a plurality of selector circuits each selecting one of first to third inputs in accordance with a control signal, and a plurality of registers associated with a plurality of the selector circuits, and receiving an output transmitted from the associated selector circuit. The selector circuits and the registers are electrically connected to one another such that when the selector circuits select the first input, the registers output a signal to be used in the logic circuit, when the selector circuits select the second input, the registers are electrically connected in series in a first direction to one another for defining a first scan path, and when the selector circuits select the third input, the registers are electrically connected in series in a second direction to one another for defining a second scan path. The first and second directions are opposite to each other.
Japanese Patent No. 2727941 (B2) (Japanese Unexamined Patent Publication No. 7-159492 (A)) has suggested a method of analyzing a failure in an integrated circuit including a plurality of flip-flops electrically connected in series to one another, a scan path for reading data out of the flip-flops in order by shift operation, and an output selector which selects and reads an output signal among output signals transmitted from the flip-flops, through an output line associated with each of the flip-flops, the method including the steps of reading data out of the scan path, reading data out of each of the flip-flops by means of the output selector, and comparing data read out of the scan path to data of he flip-flops read through the output selector, to thereby identify a failure site.
Japanese Unexamined Patent Publication No. 7-104033 (A) has suggested a method of testing LSI including a combinational circuit and N scan flip-flops. The N scan flip-flops are connected to one another such that an output Q terminal of a flip-flop is electrically connected to an input/output terminal of a next-stage flip-flop, thereby the N scan flip-flops can accomplish interactive scan operation. When a scan path circuit is in failure, data is input into LSI through the interactive input/output terminal, and then, the input data is turned inversely at each of stages of the interactive scan flip-flops. Then, the data is output to the input/output terminal to thereby detect a failure site. Then, test data is input into LSI through the interactive input/output terminal, and then, is turned inversely at an interactive scan flip-flop located prior to the failure site. Then, the test data is output to the input/output terminal. The test data is compared to expectation.
Japanese Patent No. 3104739 (B2) (Japanese Unexamined Patent Publication No. 9-281189 (A)) has suggested a LSI tester including a pattern generator having a scan path therein, a pattern comparator, a path tracer which traces back connection in a direction opposite to a direction in which signals are transmitted, based on circuit data transmitted from a first flip-flop having detected inconsistency or a first external terminal, and identifies a second flip-flop or a second external terminal to which a signal first reaches from the first flip-flop or the first external terminal, and means for varying a pattern by which inconsistency is detected, to the second flip -flop or the second external terminal.
Japanese Unexamined Patent Publication No. 11-133119 (A) has suggested an apparatus for producing test data, including a memory storing circuit data indicative of connection among logic devices, a library of logic devices, a memory storing data defining degenerate failure, a memory storing data defining conditions for carrying out scan ATPG, first means for identifying a site at which it is difficult to detect a failure, second means for identifying a site into which a failure is to be inserted, means for outputting data produced by the first and second means, and means for outputting data about a failure which is not possible to be inserted.
Japanese Unexamined Patent Publication No. 11-101859 (A) has suggested a semiconductor device including a plurality of sequence circuits by which a scan path is formed to allow a scan path test signal to pass therethrough. The semiconductor device includes a functional circuit storing or processing data, a first-stage combinational circuit located prior to the functional circuit, and receiving an output signal transmitted from a sequence circuit located prior to the functional circuit among the sequence circuits, and a switch for switching an output signal transmitted from the first-stage combinational circuit and an output signal transmitted from a combinational circuit other than the first-stage combinational circuit, based on a control signal, and outputting the selected output signal to one of the sequence circuits.
Japanese Unexamined Patent Publication No. 11-174126 (A) has suggested an apparatus for generating a pattern to be used for self-testing a logic circuit block by means of a combinational circuit. The apparatus includes a first circuit for generating a random number pattern used for testing a circuit, a first memory storing a pattern used for testing the circuit, and a selector which selects one of output signals transmitted from the first circuit and the first memory, and transmits the thus selected output signal to the circuit.